ECE484 Laboratory Exercises - Spring 2004 

Setting up the Cadence environment here at SIUE.

Getting started with Cadence here at SIUE.

·             Lab 1:   Verilog XL (Part 1)

·             Lab 2:   Verilog XL (Part 2) 

·             Lab 3:   Verilog XL (Part 3) 

·        Lab 4:   Logic Synthesis Using Ambit

·             Lab 5:   Schematic Capture and Symbol Creation Using Composer

·             Lab 6:   Simulation Using Spectre and Spectre/Verilog

·             Lab 7:   Layout and DRC Using Virtuoso (Part 1)

·             Lab 8:   Layout and DRC Using Virtuoso (Part 2)

·             Lab 9:   Extraction, LVS and Post-Layout Simulation

·             Lab 10: Hierarchical Design

·             Lab 11: Automatic Place and Route Using Silicon Ensemble

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