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Simulation in Analog Environment

Now we are ready to simulate the schematic of the hierarchical design. For this, create a new cell view in the "LogicGates" Library with the same cell name as the schematic name for the hierarchical design  i.e. "hierdsgn". Select the "Hierarchy Editor" in the "Tool" and that will automatically write down the view name for the Cell View which will be "config".

This will open the two windows as shown below

Popup Window-1

Popup Window - 2

The popup window-1 will be above the Popup Window-2.

The following entries have to be entered in the Popup Window -1

In the Entry "View" type in "schematic"

Click on "Use Template..." and a window will open which will be as shown below

In This window, select the Name to be "spectreVerilog" from the pulldown menu and click on OK.

In the Popup Window-1, in "Library List", Enter the name of the Library where the schematic of the hierarchical design resides i.e "Logicgates"

After all the above things are done, the Popup window will be as shown below

Click on "OK"

All the entries will be loaded in to the Popup Window -2. In the view to use column for the nandgate, enter  "functional" and for nor3input enter "schematic" and for the inverter the "extracted" view and click on the update( which is the 8th icon) and the window will be as shown as below.

Now click on the "open" button and this will open the schematic of the hierarchical design. To proceed with the simulation, go to the next step.